| A | Annotate the assembler output with miscellaneous debugging information.
|
| D | Dump all macro definitions, at the end of preprocessing, in addition to normal output.
|
| a | Produce all the dumps listed above
|
| m | Print statistics on memory usage, at the end of the run, to standard error.
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| p | Annotate the assembler output with a comment indicating which pattern and alternative was used. The length of each instruction is also printed.
|
| P | Dump the RTL in the assembler output as a comment before each instruction. Also turns on -dp annotation.
|
| x | Just generate RTL for a function instead of compiling it. Usually used with r.
|
| y | Dump debugging information during parsing, to standard error.
|
| r | RTL 生成 | file.00.rtl
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| i | 兄弟呼出の最適化 | file.01.sibling
|
| h | finalization of EH handling code (Exception Handling) | file.02.eh
|
| j | the first jump optimization | file.03.jump
|
| e | SSA
(static single assignment form 静的単一代入形式) 最適化 | file.04.ssa and file.07.ussa
|
| W | SSA 条件付定数伝播 | file.05.ssaccp
|
| X | SSA 未使用コード除去 | file.06.ssadce
|
| u | null pointer 除去 | file.08.null
|
| s | 式共通部分除去 CSE (common subexpression elimination) (including the jump optimization that sometimes follows CSE) | file.09.cse
|
| F | purging "ADDRESSOF" codes | file.10.addressof
|
| G | 広域 CSE (GCSE) | file.11.gcse
|
| L | ループ最適化 | file.12.loop
|
| b | 分岐確率計算 | file.14.bp
|
| f | CFG 分析 control and data flow analysis | file.14.cfg
|
| C | IF 変換 (1) | file.15.ce1
|
| T | running tracer | file.16.tracer
|
| t | the second CSE pass (including the jump optimization that sometimes follows CSE) | file.17.cse2
|
| f | Also life analysis | file.18.life
|
| c | 命令結合 instruction combination | file.19.combine
|
| N | the register move pass | file.21.regmove
|
| S | スケジューリング (1) the first scheduling pass | file.22.sched
|
| l | 局所 レジスタ割当 local register allocation | file.23.lreg
|
| g | 広域 レジスタ割当 global register allocation | file.24.greg
|
| o | post-reload optimizations | file.25.postreload
|
| w | the second flow pass | file.26.flow2
|
| z | the peephole pass | file.27.peephole2
|
| n | 仮想レジスタ番号振直し | file.28.rnreg
|
| E | IF 変換 (2) | file.29.ce3
|
| R | スケジューリング (2) | file.30.sched2
|
| k | conversion from registers to stack | file.31.stack
|
| B | block reordering | file.32.bbro
|
| M | performing the machine dependent reorganization pass | file.33.mach
|
| d | 遅延分岐のスケジューリング | file.34.dbr
|
| v | For each of the other indicated dump files (except for file.00.rtl), dump a representation of the control flow graph suitable for viewing with VCG | file.pass.vcg.
|
