Last Update: "2014/05/08 22:54:36 makoto"
7seg
http://www.csee.umbc.edu/~tinoosh/cmpe415/slides/05-Memory-examples-fifo.pdf
7seg.v
module seven_seg_decoder ( output reg [7:1] seg,
input[3:0] bcd,
blank );
always @*
case ({blank, bcd})
5'b00000: seg = 7'b0111111; // 0
5'b00001: seg = 7'b0000110; // 1
5'b00010: seg = 7'b1011011; // 2
5'b00011: seg = 7'b1001111; // 3
5'b00100: seg = 7'b1100110; // 4
5'b00101: seg = 7'b1101101; // 5
5'b00110: seg = 7'b1111101; // 6
5'b00111: seg = 7'b0000111; // 7
5'b01000: seg = 7'b1111111; // 8
5'b01001: seg = 7'b1101111; // 9
5'b01010, 5'b01011, 5'b01100,
5'b01101, 5'b01110, 5'b01111:
seg = 7'b1000000; // "-" for invalid code
default: seg = 7'b0000000; // blank
endcase
endmodule
test.v
module TEST;
reg [3:0] bcd;
reg inputblank;
wire [7:1] display;
seven_seg_decoder instance_name ( display, bcd, inputblank);
initial begin
$monitor ("%t: %b %4b %7b",
$time, inputblank, bcd, display);
bcd=4'b0000; inputblank = 0;
#10 bcd=4'b0001;
#10 bcd=4'b0010;
#10 bcd=4'b0011;
#10 bcd=4'b0100;
#10 bcd=4'b0101;
#10 bcd=4'b0110;
#10 bcd=4'b0111;
#10 bcd=4'b1000;
#10 bcd=4'b1001;
#10 bcd=4'b1010;
#10 bcd=4'b1011;
#10 bcd=4'b1100;
#10 bcd=4'b1101;
#10 bcd=4'b1110;
#10 bcd=4'b1111;
#10 bcd=4'b0000; inputblank = 1;
#10 bcd=4'b0001;
#10 bcd=4'b0010;
#10 bcd=4'b0011;
#10 bcd=4'b0100;
#10 bcd=4'b0101;
#10 bcd=4'b0110;
#10 bcd=4'b0111;
#10 bcd=4'b1000;
#10 bcd=4'b1001;
#10 bcd=4'b1010;
#10 bcd=4'b1011;
#10 bcd=4'b1100;
#10 bcd=4'b1101;
#10 bcd=4'b1110;
#10 bcd=4'b1111;
#10 $finish;
end
endmodule
compile
iverilog -g2005-sv -v -o test -s TEST 7seg.v test.v
...
...
... done
CALCULATING ISLANDS
... done, 0 seconds.
CODE GENERATION
... invoking target_design
... done, 0.01 seconds.
STATISTICS
lex_string: add_count=67 hit_count=191
exec
modena@makoto 22:41:03/140508(..verilog/7seg)% ./test
0: 0 0000 0111111
10: 0 0001 0000110
20: 0 0010 1011011
30: 0 0011 1001111
40: 0 0100 1100110
50: 0 0101 1101101
60: 0 0110 1111101
70: 0 0111 0000111
80: 0 1000 1111111
90: 0 1001 1101111
100: 0 1010 1000000
110: 0 1011 1000000
120: 0 1100 1000000
130: 0 1101 1000000
140: 0 1110 1000000
150: 0 1111 1000000
160: 1 0000 0000000
170: 1 0001 0000000
180: 1 0010 0000000
190: 1 0011 0000000
200: 1 0100 0000000
210: 1 0101 0000000
220: 1 0110 0000000
230: 1 0111 0000000
240: 1 1000 0000000
250: 1 1001 0000000
260: 1 1010 0000000
270: 1 1011 0000000
280: 1 1100 0000000
290: 1 1101 0000000
300: 1 1110 0000000
310: 1 1111 0000000
modena@makoto 22:41:28/140508(..verilog/7seg)%
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